1. Field of the Invention
This invention relates to integrated circuits and more particularly to techniques for scheduling memory requests to a memory.
2. Description of the Related Art
Referring to FIG. 1, an exemplary system-on-a-chip (i.e., SoC 102) includes multiple central processing units (i.e., CPUs, e.g., CPU0 104, CPU1 106, . . . , CPUN 108) that issue memory requests through an interface (e.g., interface A) to an integrated memory controller (e.g., DRAM controller 130). The integrated memory controller enforces system coherence and serves as a conduit to a shared memory space (e.g., DRAM 114). A specialized memory requestor, for example, a graphics processing unit (e.g., GPU 140) issues memory requests (e.g., direct memory access requests, i.e., DMA requests) to an interface of the integrated memory controller (e.g., interface B), and receives responses from that interface of the integrated memory controller. A typical DRAM controller 130 supports coherent traffic, i.e., a memory coherency protocol is implemented to maintain consistency between the copies of data accessed by CPU, I/O, and GPU requests. A typical arbitration scheme combines memory request streams in the SoC pipeline using a priority-based arbitration scheme that chooses between different request streams to schedule commands on the memory bus. Such scheduling of memory requests from those multiple requestors affects memory latency and memory bandwidth realized for each requesting source on the memory bus.